1m x 1 static ram CY7C107BN cy7c1007bn cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06426 rev. ** revised february 1, 2006 features ?high speed ?t aa = 15 ns ? cmos for optimum speed/power ? automatic power-down when deselected ? ttl-compatible inputs and outputs functional description the CY7C107BN and cy7c1007bn are high-performance cmos static rams organized as 1,048,576 words by 1 bit. easy memory expansion is provided by an active low chip enable (ce ) and three-state drivers. these devices have an automatic power-down feature that reduces power consumption by more than 65% when deselected. writing to the devices is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the input pin (d in ) is written into the memory location specified on the address pins (a 0 through a 19 ). reading from the devices is accomplished by taking chip enable (ce ) low while write enable (we ) remains high. under these conditions, the contents of the memory location specified by the address pins will appear on the data output (d out ) pin. the output pin (d out ) is placed in a high-impedance state when the device is deselected (ce high) or during a write operation (ce and we low). the CY7C107BN is available in a standard 400-mil-wide soj; the cy7c1007bn is available in a standard 300-mil-wide soj logic block diagram pin configuration top view soj 512 x 2048 arra y a 5 a 6 a 7 column decoder row decoder sense amps power down we ce input buffer d out d in a 4 a 3 a 2 a 1 a 0 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 12 13 25 28 27 26 gnd a 11 a 12 a 13 a 14 we v cc a 9 a 10 ce a 0 d out d in a 8 a 7 a 6 a 2 a 1 a 4 nc nc a 15 a 16 a 8 a 12 a 14 a 16 a 15 a 10 a 11 a 13 a 17 a 18 a 19 a 17 a 18 a 19 a 5 a 3 a 9 selection guide 7c107bn-15 7c1007bn-15 maximum access time (ns) 15 maximum operating current (ma) 80 maximum cmos standby current i sb2 (ma) 2 [+] feedback [+] feedback
CY7C107BN cy7c1007bn document #: 001-06426 rev. ** page 2 of 7 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................ .............. ....-65c to +150c ambient temperature with power applied........... .............. ............ .........-55c to +125c supply voltage on v cc relative to gnd [1] ..... -0.5v to +7.0v dc voltage applied to outputs in high z state [1] .................................... -0.5v to v cc + 0.5v dc input voltage [1] ..................................-0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .............. .............. ....... >2001v (per mil-std-883, method 3015) latch-up current ..................................................... >200 ma operating range range ambient temperature [2] v cc commercial 0c to +70c 5v 10% industrial -40c to +85c 5v 10% electrical characteristics over the operating range parameter description test conditions 7c107bn-15 7c1007bn-15 min. max. unit v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 v v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage [1] -0.3 0.8 v i ix input leakage current gnd < v i < v cc -1 +1 ma i oz output leakage current gnd < v i < v cc , output disabled ?5 +5 ma i os output short circuit current [3] v cc = max., v out = gnd -300 ma i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 80 ma i sb1 automatic ce power-down current? ttl inputs max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max 20 ma i sb2 automatic ce power-down current ? cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v, f = 0 2ma capacitance [4] parameter description test conditions max. unit c in : addresses input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 7pf c in : controls 10 pf c out output capacitance 10 pf notes: 1. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 2. t a is the ?instant on? case temperature. 3. not more than 1 output should be shorted at one time. dura tion of the short circuit shou ld not exceed 30 seconds. 4. tested initially and after any design or process changes that may affect these parameters. [+] feedback [+] feedback
CY7C107BN cy7c1007bn document #: 001-06426 rev. ** page 3 of 7 ac test loads and waveforms switching characteristics [5] over the operating range 7c107bn-15 7c1007bn-15 parameter descrip tion min. max. unit read cycle t rc read cycle time 15 ns t aa address to data valid 15 ns t oha data hold from address change 3 ns t ace ce low to data valid 15 ns t lzce ce low to low z [6] 3ns t hzce ce high to high z [6, 7] 7ns t pu ce low to power-up 0 ns t pd ce high to power-down 15 ns write cycle [8] t wc write cycle time 15 ns t sce ce low to write end 12 ns t aw address set-up to write end 12 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 12 ns t sd data set-up to write end 8 ns t hd data hold from write end 0 ns t lzwe we high to low z [6] 3ns t hzwe we low to high z [6, 7] 7ns notes: 5. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 6. at any given temperature and voltage condition, t hzce is less than t lzce and t hzwe is less than t lzwe for any given device. 7. t hzce and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is m easured 500 mv from steady-stat e voltage. 8. the internal write time of the memory is defined by the overlap of ce low and we low. ce and we must be low to initiate a wr ite, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 3.0v 5v output r1 480 ? r2 255 ? 30 pf including jig and scope gnd 90% 10% 90% 10% 3 ns 3 ns 5v output 5pf including jig and scope (a) (b) output 1.73v equivalent to: th venin equivalent all input pulses r2 255 ? r1 480 ? 167 ? [+] feedback [+] feedback
CY7C107BN cy7c1007bn document #: 001-06426 rev. ** page 4 of 7 switching waveforms read cycle no. 1 [10, 11] read cycle no. 2 [11, 12] write cycle no. 1 (ce controlled) [13] notes: 9. no input may exceed v cc + 0.5v. 10. device is continuously selected, ce = v il . 11. we is high for read cycle. 12. address valid prior to or coincident with ce transition low. 13. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t lzce t pu high impedance t hzce t pd high i cc i sb impedance address ce data out v cc supply current data valid t sce t aw t sa t pwe t ha t hd t sd t wc high impedance address ce we data out data in [+] feedback [+] feedback
CY7C107BN cy7c1007bn document #: 001-06426 rev. ** page 5 of 7 write cycle no. 2 (we controlled) [13] truth table ce we d out mode power h x high z power-down standby (i sb ) l h data out read active (i cc ) l l high z write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 15 CY7C107BN-15vc 51-85032 28-lead (400-mil) molded soj commercial cy7c1007bn-15vc 51-85031 28-lead (300-mil) molded soj cy7c1007bn-15vxc 51-85031 28-lead (300-mil) molded soj (pb-free) CY7C107BN-15vi 51-85032 28-lead (400-mil) molded soj industrial please contact local sales representative regarding availability of these parts switching waveforms (continued) t wc data valid data undefined high impedance t sce t aw t sa t pwe t ha t hd t hzwe t lzwe t sd address ce we data out data in [+] feedback [+] feedback
CY7C107BN cy7c1007bn document #: 001-06426 rev. ** page 6 of 7 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product or company names mentioned in this docum ent may be the trademarks of their respective holders. package diagrams 51-85032-*b pin 1 i.d .435 .395 .445 .405 .128 .148 .360 .380 .026 .015 .032 .020 dimensions in inches min. max. .025 min. .007 .013 .050 typ. .720 .730 1 14 15 28 0.004 seating plane 51-85032.*b 28-lead (400-mil) molded soj (51-85032) min. max. pin 1 id 0.291 0.300 0.050 typ. 0.007 0.013 0.330 0.350 0.120 0.140 0.025 min. 0.262 0.272 0.697 0.713 0.013 0.019 0.014 0.020 0.032 0.026 a a detail external lead design option 1 option 2 1 14 15 28 0.004 seating plane note : 1. jedec std ref mo088 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.006 in (0.152 mm) per side 3. dimensions in inches 51-85031-*c 28-lead (300-mil) molded soj (51-85031) [+] feedback [+] feedback
CY7C107BN cy7c1007bn document #: 001-06426 rev. ** page 7 of 7 document history page document title: CY7C107BN/cy7c1007bn 1m x 1 static ram document number: 001-06426 rev. ecn no. issue date orig. of change description of change ** 423847 see ecn nxr new data sheet [+] feedback [+] feedback
|
